As is well known, existing DVD systems such as a DVD player, DVD-R and DVD-RW drives, and MPEG (Moving Picture Experts Group) format systems require multiple reference frequency clocks. These reference frequency clocks include at least a first series of reference frequency clocks for video use based on a 27 MHz clock (the series referred to as 27 MHz first clock series), a second series of reference frequency clocks for audio use based on a 33.8688 MHz clock (particularly for CDs, having frequencies that are integral multiples of 44.1 kHz sampling frequency, referred to as 33.8688 MHz second reference frequency clock series), and a third series of reference frequency clocks for audio use based on a 36.864 MHz clock (particularly for DVDs, having frequencies that are integral multiples of 48 kHz and 32 kHz sampling frequencies, referred to as third 36.864 MHz third reference frequency clock series).
Each of these three reference frequency clock series can be obtained using a respective oscillation module. In this approach, however, one oscillation module must be provided for each reference frequency, which results in an increase of cost of the clock generation system.
Conventionally, in order to reduce the cost, use is made of a well-known PLL (Phase Locked Loop) circuit to generate two of the three reference frequency clock series from one reference frequency clock.
Referring to FIG. 5, there is shown a clock generation system in accordance with related art. This clock generation system utilizes one of the three reference frequency clocks to generate the rest of the reference frequency clock series by means of two PLL circuits. The clock generation system shown in FIG. 5 was devised by the present inventor in the process of developing the inventive system, and has not been disclosed to the public. Therefore, the clock generation system shown in FIG. 5 is not prior art.
The clock generation system of FIG. 5 generates a second series Fr2s of reference frequency clocks (33.8688 MHz series) and a third series Fr3s of reference frequency clocks (36.864 MHz series) from a first reference frequency clock Fr1 (27 MHz) generated by an oscillation module.
A first PLL circuit 50a of FIG. 5 has a first frequency divider 51a for frequency-dividing the 27 MHz first reference frequency clock Fr1 inputted thereto by a frequency division factor of 625. The divided clock is supplied to a phase comparator (PD) 53a as a comparison input P1 thereto. A second frequency divider 52a frequency-divides the output of the PLL circuit 50a by 3136, and supplies the resultant clock to the phase comparator 53a as another comparison input P2 thereto. The phase comparator 53a compares the phases of the two comparison inputs P1 and P2, to generate a comparison output in accord with the phase difference between them. The comparison output is smoothed by a low-pass filter (LPF) 54a before it is supplied as a control input to a controllable oscillator (e.g. voltage controlled oscillator: VCO) 55a. The frequency of the voltage controlled oscillator 55a is controlled by the control input so as to cause the two inputs of the phase comparator 53a to have the same frequency and to be in phase. The loop gain of the PLL circuit is so large that the control deviation that remains is very small. Thus, the frequency of the output of the voltage controlled oscillator 55a is converted to 135.4752(=27×3136/625) MHz in accord with the frequency division factors of the frequency dividers 51a and 52a. 
The output of the voltage controlled oscillator 55a is frequency-divided by a frequency divider 56a by a factor of 4 to generate a second reference frequency clock Fr2. The output of the voltage controlled oscillator 55a is further frequency-divided by a ⅙-frequency divider 57a, ⅛-frequency divider 58a, and 1/12-frequency divider 59a to generate 22.5792 MHz, 16.9344 MHz, and 11.2896 MHz clocks, respectively. These frequencies have specific frequency ratios relative to the second reference frequency clock Fr2. Together with the second reference frequency clock Fr2, these clocks constitute the second series Fr2s of reference frequency clocks for use in CD sampling, all having integral multiples of 44.1 kHz CD sampling frequency.
A second PLL circuit 50b also performs similar frequency division to that of the first PLL circuit 50a, except that the frequency division ratio of the first frequency divider 51b is 1/375, while that of the second frequency divider 52b is 1/2048. The frequency of the output of the voltage controlled oscillator 55b is converted to 147.456 (=27×2048/375) MHz in accord with the frequency division ratios of the frequency dividers 51b and 52b. Incidentally, reference numeral 53b indicates a phase comparator, and 54b a low-pass filter.
The output of the voltage controlled oscillator 55b is frequency-divided by a frequency divider 56b by a factor of 4 to produce a third reference frequency clock Fr3. In addition, the output of the voltage controlled oscillator 55b is further frequency-divided by a ⅙-frequency divider 57b, a ⅛-frequency divider 58b, and a 1/12-frequency divider 59b to generate further clocks having frequencies of 24.576 MHz, 18.432 MHz, and 12.288 MHz, respectively, which have specific frequency ratios relative to the third reference frequency clock Fr3. These reference frequency clocks constitute the third reference frequency clock series Fr3s. Each of the third reference frequency clock series Fr3s has a frequency that is an integral multiple of DVD audio sampling frequencies, 48 kHz and 32 kHz.
The first reference frequency clock series Fr1s includes the first reference frequency clock Fr1 and a 13.5 MHz clock obtained by frequency-dividing the first reference frequency clock Fr1 by a ½-frequency divider 56c. 
Thus, one may choose necessary frequency clocks from the first through third reference frequency clock series Frls-Fr3s for his use.
The S/N (signal-to-noise) ratios of the clocks generated by the clock generation system shown in FIG. 5 can be obtained using a known S/N theory as follows. As an example, the S/N ratios of the clocks belonging to the second reference frequency clock series Fr2s will be discussed. When the first reference frequency clock Fr1 is frequency-divided by 625, the S/N ratio of the frequency-divided clock is improved by 20log625 [dB]. Hence, theoretically, the S/N ratio [dB] of the output signal of the first frequency divider 51a will be equal to (S/N ratio [dB] of the first reference frequency clock+20log625) [dB]. Assuming that the S/N ratio of the first reference frequency clock is 80 [dB], the S/N ratio of the output signal will be 80+56=136 [dB]. Note that the S/N ratios are rounded off (the same is true in the discussion below).
It should be noted, however, that since the PLL circuit is in operation on the noise floor of an IC (integrated circuit) on which the PLL circuit is formed, the S/N ratio of the PLL circuit is limited by the S/N ratio of the noise floor. The S/N ratio of the noise floor is governed by the fluctuations of the power supply potential, which is on the order of 90 [dB]. Hence, the S/N ratio of the PLL circuit is limited by the S/N ratio (90 [dB]) of the noise floor. Hence, the S/N ratio [dB] of the output of the first frequency divider 51a, that is one comparison input P1 to the PD 53a, is at best 90 [dB].
Since the S/N ratios [dB] of the comparison inputs P1 and P2 to the phase comparator 53a are the same, the S/N ratio of the comparison input P2 is 90 [dB]. The S/N ratio of the comparison input to the second frequency divider 52a is lowered by 20log3136 [dB], since the comparison input P2 is multiplied accordingly by 3136. Thus, the S/N ratio [dB] of the input to the second frequency divider 52a becomes 90 [dB] of the comparison input P2 minus 20log3136 [dB], or 20.3 [dB].
Thus, the S/N ratios of the clocks belonging to the second reference frequency clock series Fr2s are 32.3 [dB] for the second reference frequency clock Fr2, 35.8 [dB] for the 22.5792 MHz clock, 38.3 [dB] for the 16.9344 MHz clock, and 41.8 [dB] for the 11.2896 MHz clock.
Similar calculations give the S/N ratios of the clocks of the third reference frequency clock series Fr3s to be 36.0 [dB] for the third reference frequency clock Fr3; 39.5 [dB] for the 24.576 MHz clock; 42.0 [dB] for the 18.432 MHz clock; and 45.5 [dB] for the 12.288 MHz clock.
In this way, using PLL circuits and frequency dividers as shown in FIG. 5, it is possible to generate second reference frequency clock series Fr2s that includes the second reference frequency clock Fr2 having a predetermined frequency, and a third reference frequency clock series Fr3s that includes the third reference frequency clock Fr3 having another predetermined frequency, all of the clocks belonging to the second and third series Fr2s and Fr3s respectively having predetermined frequency ratios relative to the first reference frequency clock Fr1. However, the S/N ratios of the clocks belonging to the second and third reference frequency clock series are lowered to between 30 [dB] and 40 [dB]. Since clocks for use in DVD systems in general require an S/N ratio of at least 50 [dB], preferably more than 60 [dB]. Therefore, deterioration in S/N ratio is a problem that must be solved.